{"id":1022,"date":"2022-03-15T17:42:10","date_gmt":"2022-03-15T21:42:10","guid":{"rendered":"https:\/\/www.ecsdump.net\/?page_id=1022"},"modified":"2022-03-15T17:42:10","modified_gmt":"2022-03-15T21:42:10","slug":"real-time-clock-cmos-setup-reference","status":"publish","type":"page","link":"https:\/\/www.ecsdump.net\/?page_id=1022","title":{"rendered":"Real Time Clock \/ CMOS Setup Reference"},"content":{"rendered":"\n<pre class=\"wp-block-code\"><code>Version: 10 March 1993\nBy Tom Przeor<\/code><\/pre>\n\n\n\n<p>AT model was the first in IBM PC family to keep track of time while switched off. The designers used Motorola MC146818 Real Time Clock (RTC from now on) chip. This chip provides clock and calendar functions, few registers to program the chip itself and some 50 bytes of general purpose memory. Typically the RTC chip is used only on power on &#8211; the BIOS will initialize the <a href=\"https:\/\/en.wikipedia.org\/wiki\/Disk_operating_system\" data-internallinksmanager029f6b8e52c=\"2\" title=\"DOS\" target=\"_blank\" rel=\"noopener\">DOS<\/a> clock and verify the<br>configuration. The RTC chip is capable of generating interrupts at specified frequency or time &#8211; we&#8217;ll get back to it later.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">RTC BIOS interface.<\/h2>\n\n\n\n<p>AT BIOS provides a number of basic functions to use RTC. The following short list should provide enough information to use them:<\/p>\n\n\n\n<p>RAM data areas used by RTC:<\/p>\n\n\n\n<p><code>Addr hex  Size<br>0040:0098 4 bytes far pointer to user wait flag<br>0040:009C 4 bytes wait count<br>0040:00A0 1 byte wait active flag:<br>bit 7 - 1 when wait time elapsed<br>bit 0 - 1 when wait active<br>bits 6-1 - reserved<\/code><\/p>\n\n\n\n<p><span style=\"text-decoration: underline;\">Int 1Ah function 02h &#8211; Get RTC time<\/span><br><code>entry: AH = 02h<br>exit:  CF clear if successful, set on error<br>CH = hour (BCD)<br>CL = minutes (BCD)<br>DH = seconds (BCD)<br>DL = daylight savings flag<br>(00h standard time, 01h daylight time)<\/code><\/p>\n\n\n\n<p><span style=\"text-decoration: underline;\">Int 1Ah function 03h &#8211; Set RTC time<\/span><br><code>entry: AH = 03h<br>CH = hour (BCD)<br>CL = minutes (BCD)<br>DH = seconds (BCD)<br>DL = daylight savings flag (as above)<br>exit: none<\/code><\/p>\n\n\n\n<p><code><span style=\"text-decoration: underline;\">Int 1Ah function 04h - Get RTC date<\/span><br>entry: AH = 04h<br>exit: CF clear if successful, set on error<br>CH = century (BCD)<br>CL = year (BCD)<br>DH = month (BCD)<br>DL = day (BCD)<\/code><\/p>\n\n\n\n<p><code><span style=\"text-decoration: underline;\">Int 1Ah function 05h - Set RTC date<\/span><br>entry: AH = 05h<br>CH = century (BCD)<br>CL = year (BCD)<br>DH = month (BCD)<br>DL = day (BCD)<br>exit: none<\/code><\/p>\n\n\n\n<p>Int 1Ah function 06h &#8211; Set RTC alarm<br>entry: AH = 06h<br><code>CH = hour (BCD)<br>CL = minutes (BCD)<br>DH = seconds (BCD)<br>exit: CF clear if successful, set on error<br>note: place address for alarm routine in interrupt 4Ah<br>vector before using this service, the alarm occurs<br>every 24 hours until turned off, invoking int 4Ah<br>each time.<\/code><\/p>\n\n\n\n<p><code>Int 1Ah function 07h - Reset RTC alarm<br>entry: AH = 07h<br>exit: none<br>note: disables alarm set with int1Ah\/fn 06h. Don't forget<br>to restore old int 4Ah vector.<\/code><\/p>\n\n\n\n<p><code>Int 15h function 83h - Set\/Cancel Wait Interval<br>subfunction 0 - Set Wait Interval<br>entry: AH = 83h<br>AL = 00h<br>CX:DX = microseconds to delay<br>ES:BX -> byte whose high bit is to be set at end of<br>interval<br>exit: CF clear if successful, set on error<\/code><\/p>\n\n\n\n<p>I<code>nt 15h function 83h - Set\/Cancel Wait Interval<br>subfunction 1 - Cancel Wait Interval<br>entry: AH = 83h<br>AL = 01h<br>exit: CF clear if successful, set on error<br>error status in AH:<br>80h invalid command (PC,PCjr)<br>86h function not supported (XT and later)<\/code><\/p>\n\n\n\n<p>In<code>t 15h function 86h - Wait<br>e<\/code>ntry: AH = 86h<br>CX:DX = interval in microseconds<br>exit: CF clear if successful (wait interval elapsed)<br>CF set on error or AH=83h wait already in progress<\/p>\n\n\n\n<p>There is a difference between functions 83h and 86h. Function 83h sets a wait interval and allows processing to continue. When the wait interval ends the user specified flag (pointed by ES:BX) is set<br>and it is software responsibility to check that flag. That function can be stopped. Function 86h on the other hand suspends any processing until specified time interval is elapsed (and cannot be stopped). These two functions share the same data areas and cannot be used at the same time. Also note that their resolution is 977 microseconds.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Direct Access to RTC chip.<\/h2>\n\n\n\n<p>RTC chip can be accessed through I\/O ports 70h and 71h. To read a byte from the chip, do an OUT 70h,addr; followed by IN al,71H. To write a byte to chip, do an OUT 70h,addr; followed by OUT 71h,value. <\/p>\n\n\n\n<p>Example: read equipment byte from CMOS info<\/p>\n\n\n\n<p><code>mov al,14h   ; register 14h holds equipment byte<br>out 70h,al   ; select address 14h on RTC chip<br>jmp $+2      ; a slight delay to settle things<br>in al,71h    ; AL now has equipment byte<\/code><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>NOTE: Original MC146818 has 64 registers (00h to 3Fh). Most of the computers used today have a RTC functional equivalent incorporated in their &#8216;chipset&#8217; and it can have more registers. Those extra bits are often used by chipset and BIOS designers to store extra information about things like DRAM wait states, refresh, m\/b cache or user defined hard drive parameters &#8211; don&#8217;t fiddle with them or you might end up in trouble. Also leave alone the reserved bytes.<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">The RTC Registers.<\/h2>\n\n\n\n<p>The registers can be divided into three functional groups:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>Clock\/calendar &#8211; updated from on chip clock, on IBM compatibles all quantities are stored in BCD format (ie. 23dec is stored 23h).<\/li><li>Status &#8211; they affect working of RTC chip itself.<\/li><li>CMOS configuration data &#8211; general purpose memory not affected and not affecting the RTC chip.<\/li><\/ol>\n\n\n\n<p>Here is detailed list of registers (all byte sized, addr in hex):<\/p>\n\n\n\n<p>Addr Function<br>==== =========================================<\/p>\n\n\n\n<p>** clock\/calendar<\/p>\n\n\n\n<p>00 current second for real-time clock<br>01 alarm second<br>02 current minute<br>03 alarm minute<br>04 current hour<br>05 alarm hour<br>06 current day of week (1=Sunday)<br>07 current date of month<br>08 current month<br>09 current year (final two digits; eg, 93)<\/p>\n\n\n\n<p>** status<\/p>\n\n\n\n<p>0A Status Register A &#8211; Read\/Write except UIP<br>== =========================================<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u013f<br>\ufffd 7 \ufffd 6 \ufffd 5 \ufffd 4 \ufffd 3 \ufffd 2 \ufffd 1 \ufffd 0 \ufffd<br>\ufffd UIP \ufffd DV2 \ufffd DV1 \ufffd DV0 \ufffd RS3 \ufffd RS2 \ufffd RS1 \ufffd RS0 \ufffd<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>    bit 7 - UIP flag, Update In Progress. When set an update\n    cycle is in progress and the clock\/calendar cannot be\n    accessed. When clear, at least 244 microseconds are\n    available to access clock\/calendar bytes (it's plenty of\n    time even on 6MHz AT).\n\n    bits 6-4 - divider bits that define RTC operating frequency.\n    ATs have a 32.768 kHz (wrist watch) crystal to operate RTC\n    and divider should be set to '010', other values will make a\n    time machine from your computer.\n\n    bits 3-0 - Rate Selection bits that define the periodic\n    interrupt rate, see another table for details. Default value\n    set by BIOS is '0110'.<\/code><\/pre>\n\n\n\n<p>0B Status Register B &#8211; Read\/Write<br>== ==============================<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u013f<br>\ufffd 7 \ufffd 6 \ufffd 5 \ufffd 4 \ufffd 3 \ufffd 2 \ufffd 1 \ufffd 0 \ufffd<br>\ufffd SET \ufffd PIE \ufffd AIE \ufffd UIE \ufffd SQWE\ufffd DM \ufffd24\/12\ufffd DSE \ufffd<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>    bit 7 (SET) - when set to 1, any update in progress is\n    aborted and a program may initialize the\n    clock\/calendar\/alarm bytes without an update occurring.\n    Setting this bit clears UIE (bit 4). Clearing bit 7 allows\n    the update cycle to continue.\n\n    bit 6 (PIE) - Periodic Interrupt Enable, when set the\n    periodic interrupt will occur at the frequency specified by\n    RS bits in Status Register A.\n\n    bit 5 (AIE) - Alarm Interrupt Enable, when set the alarm\n    interrupt will be asserted once for each second that the\n    current time matches the alarm time.\n\n    bit 4 (UIE) - Update-ended Interrupt Enable, when set the\n    update-ended interrupt will be asserted once each second\n    after the end of update cycle. This bit is cleared when SET\n    bit goes high but it is not reset when SET is cleared.\n\n    bit 3 (SQWE) - Square Wave Enable, when set, enables the\n    square wave output on the SQW pin at the frequency specified\n    by the RS bits in the Status Register A. The SQW pin is not\n    connected to anything in the AT.\n\n    bit 2 (DM) - Data Mode, indicates mode for clock\/calendar\n    data: 0=BCD and 1=binary, BIOS setting is 0.\n\n    bit 1 (24\/12) - controls hours byte, 0=12-hour and 1=24-hour\n    format, BIOS setting is 1.\n\n    bit 0 (DSE) - Daylight Savings Enable, when set two special\n    updates will occur: last Sunday in April time will go\n    01:59:59 &gt; 03:00:00 and last Sunday in October 01:59:59 &gt;\n    01:00:00. BIOS sets it to 0 (ie. no daylight saving).<\/code><\/pre>\n\n\n\n<p>0C Status Register C &#8211; Read-only<br>== =============================<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u013f<br>\ufffd 7 \ufffd 6 \ufffd 5 \ufffd 4 \ufffd 3 \ufffd 2 \ufffd 1 \ufffd 0 \ufffd<br>\ufffd IRQF\ufffd PF \ufffd AF \ufffd UF \ufffd 0 \ufffd 0 \ufffd 0 \ufffd 0 \ufffd<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>    bit 7 (IRQF) - Interrupt Request Flag, when set one of the\n    interrupts enabled in Status Register B has occurred.\n\n    bit 6 (PF) - Periodic interrupt Flag, when set the periodic\n    interrupt has occurred.\n\n    bit 5 (AF) - Alarm interrupt Flag, when set the alarm\n    interrupt has occurred.\n\n    bit 4 (UF) - Update-ended interrupt Flag, when set the\n    update-ended alarm interrupt has occurred.\n\n    NOTE: PF, AF, UF are set regardless of corresponding enable\n    bits in Status Register B. IRQF will be set only if the\n    interrupt flag and its corresponding enable bit are set.\n    These four flags are cleared each time Status Register C is\n    read.\n\n    bits 3-0 - reserved, always 0.<\/code><\/pre>\n\n\n\n<p>0D Status Register D &#8211; Read-only<br>== =============================<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u013f<br>\ufffd 7 \ufffd 6 \ufffd 5 \ufffd 4 \ufffd 3 \ufffd 2 \ufffd 1 \ufffd 0 \ufffd<br>\ufffd VRT \ufffd 0 \ufffd 0 \ufffd 0 \ufffd 0 \ufffd 0 \ufffd 0 \ufffd 0 \ufffd<br>\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>    bit 7 (VRT) - Valid RAM and Time, OK when set, when clear\n    indicates power was lost.\n\n    bits 6-0 - reserved.<\/code><\/pre>\n\n\n\n<p>** configuration<\/p>\n\n\n\n<p>0E POST diagnostics status byte<br>== ============================<br>bit 7 = 1 clock lost power<br>bit 6 = 1 CMOS checksum bad<br>bit 5 = 1 invalid configuration found at POST<br>bit 4 = 1 memory size compare error at POST<br>bit 3 = 1 fixed disk or controller failed<br>bit 2 = 1 invalid RTC time (eg. 31 Feb)<br>bits 1-0 &#8211; reserved<\/p>\n\n\n\n<p>0F Shutdown Status Byte<br>== ====================<br>This byte is read upon startup after CPU reset in order to<br>determine if the reset cause (to get out of protected mode<br>etc.)<br>00 &#8211; power on reset<br>(0 = soft reset (Ctrl-Alt-Del) or unexpected shutdown. Skip<br>POST) &#8211; conflicting info from older reference ??????<br>01 &#8211; memory size pass<br>02 &#8211; memory test pass<br>03 &#8211; memory test fail<br>04 &#8211; POST end, boot system<br>05 &#8211; JMP DWORD PTR 0:[0467h] with EOI (End Of Interrupt)<br>06 &#8211; protected tests pass<br>07 &#8211; protected tests fail<br>08 &#8211; memory size fail<br>09 &#8211; INT 15h block move<br>0A &#8211; JMP DWORD PTR 0:[0467h] without EOI<\/p>\n\n\n\n<p>10 Diskette drive types<br>== ====================<br>bits 7-4 &#8211; drive 0 type (A:)<br>bits 3-0 &#8211; drive 1 type (B:)<br>0000b &#8211; no drive<br>0001b &#8211; 360k<br>0010b &#8211; 1.2M<br>0011b &#8211; 720k<br>0100b &#8211; 1.44M<\/p>\n\n\n\n<p>11 Reserved<br>12 Hard disk drive type<br>== ====================<br>(for drives C: and D:, when between 1 and 14)<br>bits 7-4 &#8211; fixed disk 0 type (C:)<br>bits 3-0 &#8211; fixed disk 1 type (D:)<br>0000b = no drive<br>0001b-1110b = drive type<br>1111b = drive 0 (1) type stored at addr 19h (1Ah)<br>13 Reserved<br>14 Equipment byte<br>== ==============<br>bits 7-6 &#8211; no. of floppy drives (00=1, 01=2, 10=3, 11=4)<br>bits 5-4 &#8211; primary display 00 = none, EGA, VGA \u2026<br>01 = 40&#215;25 colour<br>10 = 80&#215;25 colour<br>11 = 80&#215;25 monochrome<br>bits 3-2 &#8211; reserved<br>bit 1 =1 if math copro installed<br>bit 0 =1 if floppy drive(s) present<\/p>\n\n\n\n<p>15 Base memory (low byte)<br>16 Base memory (high byte)<br>== =======================<br>in kbytes (eg. 0100H=256K, 0200H=512K, 0280H=640K)<\/p>\n\n\n\n<p>17 Extended memory above 1M (low byte)<br>18 Extended memory (high byte) in kbytes<\/p>\n\n\n\n<p>19 Disk 0 type if (CMOS addr 12H &amp; 0fH) is 0fH<br>1A Disk 1 type if (CMOS addr 12H &amp; f0H) is f0H<\/p>\n\n\n\n<p>1B-2D Reserved<\/p>\n\n\n\n<p>2E Checksum of CMOS addresses 10H through 20H (high byte)<br>2F Checksum of CMOS addresses 10H through 20H (low byte)<\/p>\n\n\n\n<p>30 Actual extended memory size (low byte) ???<br>31 Actual extended memory size (high byte) ???<\/p>\n\n\n\n<p>32 Century in BCD (eg. 19h)<\/p>\n\n\n\n<p>33 Miscellaneous flags<br>bit 7 &#8211; IBM 128K memory option installed<br>bit 6 &#8211; used by &#8220;Setup&#8221; utility (?)<br>bits 5-0 &#8211; reserved<\/p>\n\n\n\n<p>34-3F Reserved<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Using RTC hardware interrupt.<\/h2>\n\n\n\n<p>RTC interrupt pin is connected to IRQ8 line in AT bus and generates int 70h when enabled. The chip can generate three different types of interrupts: periodic, alarm and update-ended. To use RTC interrupt<br>first install interrupt service routine and point int 70h vector to it, then program RTC status registers (details shortly) and &#8216;unmask&#8217; bit 0 of second PIC&#8217;s mask register at port A1h. You can enable more<br>than one interrupt type at the same time, in that case your interrupt handler should check which type has occurred (by reading Status Register C).<\/p>\n\n\n\n<h1 class=\"wp-block-heading\">Update-Ended Interrupt<\/h1>\n\n\n\n<p>This is the simplest type &#8211; interrupt is generated after each clock update exactly every 1 second. To enable set bit 4 (UIE) in Status Register B.<\/p>\n\n\n\n<h1 class=\"wp-block-heading\">Alarm Interrupt<\/h1>\n\n\n\n<p>This is a second type &#8211; it generates interrupt at specified time. To use it first set Alarm Seconds (addr 01h), Alarm Minute (addr 03h) and Alarm Hour (addr 05h), then set bit 5 (AIE) in Status Register<br>B. The special value FFh in one of alarm registers will match any time, eg. FF:FF:00 will generate alarm interrupt every minute, FF:00:FF will generate interrupt every second during first minute of every hour.<\/p>\n\n\n\n<h1 class=\"wp-block-heading\">Periodic Interrupt<\/h1>\n\n\n\n<p>The frequency of this interrupt is programmable from 2 to 8192 per second. To use this type of interrupt first set RS (Rate Select) bits in Status Register A to the required value:<\/p>\n\n\n\n<p>RS Int\/sec Period<br>3210 &#8211; &#8211;<br>0000 none none<br><code>0001 256 3.90625 ms<br>0010 128 7.8125 ms<br>0011 8192 122.070 Micros<br>0100 4096 244.141 Micros<br>0101 2048 488.281 Micros<br>0110 1024 976.562 Micros<br>0111 512 1.93125 ms<br>1000 256 3.90625 ms<br>1001 128 7.8125 ms<br>1010 64 15.625 ms<br>1011 32 31.25 ms<br>1100 16 62.50 ms<br>1101 8 125.0 ms<br>1110 4 250.0 ms<br>1111 2 500.0 ms<\/code><\/p>\n\n\n\n<p>Note: usually this is set to 0110 by BIOS at boot up.<\/p>\n\n\n\n<p>After setting RS bits set bit 6 (PIE) in Status Register B.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>AT model was the first in IBM PC family to keep track of time while switched off. The designers used Motorola MC146818 Real Time Clock (RTC from now on) chip. This chip provides clock and calendar functions, few registers to program the chip itself and some 50 bytes of general purpose memory. Typically the RTC&hellip;<\/p>\n<p><a class=\"more-link\" href=\"https:\/\/www.ecsdump.net\/?page_id=1022\" title=\"Continue reading &lsquo;Real Time Clock \/ CMOS Setup Reference&rsquo;\">Continue reading <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"categories":[],"tags":[109],"wf_page_folders":[],"class_list":["post-1022","page","type-page","status-publish","hentry","tag-cmos"],"jetpack_sharing_enabled":true,"jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=\/wp\/v2\/pages\/1022","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1022"}],"version-history":[{"count":0,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=\/wp\/v2\/pages\/1022\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1022"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1022"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1022"},{"taxonomy":"wf_page_folders","embeddable":true,"href":"https:\/\/www.ecsdump.net\/index.php?rest_route=%2Fwp%2Fv2%2Fwf_page_folders&post=1022"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}