{"id":338,"date":"2015-07-24T06:13:18","date_gmt":"2015-07-24T10:13:18","guid":{"rendered":"http:\/\/72.167.111.237\/wpecsdump\/?page_id=338"},"modified":"2020-12-09T06:22:45","modified_gmt":"2020-12-09T11:22:45","slug":"82538254-pit-programmable-interval-time","status":"publish","type":"page","link":"https:\/\/www.ecsdump.net\/?page_id=338","title":{"rendered":"8253\/8254 PIT – Programmable Interval Time"},"content":{"rendered":"

Original source: http:\/\/heim.ifi.uio.no\/~stanisls\/helppc\/8253.html<\/a><\/em><\/p>\n

Spec documentation:  8254 PROGRAMMABLE INTERVAL TIMER<\/a><\/p>\n

Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
\nPort 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
\nPort 42h, 8253 Counter 2 Cassette and Speaker Functions
\nPort 43h, 8253 Mode Control Register, data format:<\/div>\n
\n
\t|7|6|5|4|3|2|1|0|  Mode Control Register\n\t | | | | | | | `---- 0=16 binary counter, 1=4 decade BCD counter\n\t | | | | `--------- counter mode bits\n\t | | `------------ read\/write\/latch format bits\n\t `--------------- counter select bits (also 8254 read back command)<\/pre>\n<\/div>\n
Bits
\n76 Counter Select Bits
\n00 select counter 0
\n01 select counter 1
\n10 select counter 2
\n11 read back command (8254 only, illegal on 8253, see below)<\/div>\n
Bits
\n54 Read\/Write\/Latch Format Bits
\n00 latch present counter value
\n01 read\/write of MSB only
\n10 read\/write of LSB only
\n11 read\/write LSB, followed by write of MSB<\/div>\n
Bits
\n321 Counter Mode Bits
\n000 mode 0, interrupt on terminal count; countdown, interrupt,<\/p>\n
then wait for a new mode or count; loading a new count in the
\nmiddle of a count stops the countdown<\/div>\n
001 mode 1, programmable one-shot; countdown with optional<\/p>\n
restart; reloading the counter will not affect the countdown
\nuntil after the following trigger<\/div>\n
010 mode 2, rate generator; generate one pulse after ‘count’ CLK<\/p>\n
cycles; output remains high until after the new countdown has
\nbegun; reloading the count mid-period does not take affect
\nuntil after the period<\/div>\n
011 mode 3, square wave rate generator; generate one pulse after<\/p>\n
‘count’ CLK cycles; output remains high until 1\/2 of the next
\ncountdown; it does this by decrementing by 2 until zero, at
\nwhich time it lowers the output signal, reloads the counter
\nand counts down again until interrupting at 0; reloading the
\ncount mid-period does not take affect until after the period<\/div>\n
100 mode 4, software triggered strobe; countdown with output high<\/p>\n
until counter zero; at zero output goes low for one CLK
\nperiod; countdown is triggered by loading counter; reloading
\ncounter takes effect on next CLK pulse<\/div>\n
101 mode 5, hardware triggered strobe; countdown after triggering<\/p>\n
with output high until counter zero; at zero output goes low
\nfor one CLK period<\/div>\n<\/div>\n
Read Back Command Format (8254 only)<\/div>\n
\n
\t|7|6|5|4|3|2|1|0| Read Back Command (written to Mode Control Reg)\n\t | | | | | | | `--- must be zero\n\t | | | | | | `---- select counter 0\n\t | | | | | `----- select counter 1\n\t | | | | `------ select counter 2\n\t | | | `------- 0 = latch status of selected counters\n\t | | `-------- 0 = latch count of selected counters\n\t `----------- 11 = read back command<\/pre>\n<\/div>\n
Read Back Command Status (8254 only, read from counter register)<\/div>\n
\n
\t|7|6|5|4|3|2|1|0|  Read Back Command Status\n\t | | | | | | | `--- 0=16 binary counter, 1=4 decade BCD counter\n\t | | | | `-------- counter mode bits (see Mode Control Reg above)\n\t | | `----------- read\/write\/latch format (see Mode Control Reg)\n\t | `------------ 1=null count (no count set), 0=count available\n\t `------------- state of OUT pin (1=high, 0=low)<\/pre>\n<\/div>\n