{"id":680,"date":"2020-12-05T16:06:11","date_gmt":"2020-12-05T16:06:11","guid":{"rendered":"https:\/\/www.ecsdump.net\/?page_id=680"},"modified":"2020-12-09T06:23:22","modified_gmt":"2020-12-09T11:23:22","slug":"pic-ing","status":"publish","type":"page","link":"https:\/\/www.ecsdump.net\/?page_id=680","title":{"rendered":"PIC–ing"},"content":{"rendered":"\n

Ref:<\/strong> www.jamesmolloy.co.uk https:\/\/wiki.osdev.org\/8259_PIC \/ http:\/\/www.brokenthorn.com\/Resources\/OSDevPic.html<\/p>\n\n\n\n

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The IBM PC 8259 PIC Architecture<\/strong>
In the beginning (IBM PC and XT), only a single 8259 PIC chip was used, which provided 8 IRQs to the system. These were traditionally mapped by the BIOS to interrupts 8 to 15 (0x08 to 0x0F). It is unlikely that any of these single-PIC machines will be encountered these days.<\/p>\n\n\n\n


The IBM PC\/AT 8259 PIC Architecture<\/strong>
The IBM PC\/AT extended the PC architecture by adding a second 8259 PIC chip. This was possible due to the 8259A’s ability to cascade interrupts, that is, have them flow through one chip and into another. This gives a total of 15 interrupts. Why 15 and not 16? That’s because when you cascade chips, the PIC needs to use one of the interrupt lines to signal the other chip.
The low-level concepts behind external interrupts are not very complex. All devices that are interrupt-capable have a line connecting them to the PIC (programmable interrupt controller). The PIC is the only device that is directly connected to the CPU’s interrupt pin. It is used as a multiplexer, and has the ability to prioritize between interrupting devices. It is, essentially, a glorified 8-1 multiplexer. At some point, someone somewhere realized that 8 IRQ lines just wasn’t enough, and they daisy-chained another 8-1 PIC beside the original. So in all modern PCs, you have 2 PICs, the master and the slave, serving a total of 15 interruptable devices (one line is used to signal the slave PIC).
Only hardware interrupts are handled through the Programmable Interrupt Controller. The special, CPU-dedicated interrupts are shown below.
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0 – Division by zero exception
1 – Debug exception
2 – Non maskable interrupt
3 – Break-point exception
4 – ‘Into detected overflow’
5 – Out of bounds exception
6 – Invalid opcode exception
7 – No co-processor exception
8 – Double fault (pushes an error code)
9 – Co-processor segment overrun
10 – Bad TSS (pushes an error code)
11 – Segment not present (pushes an error code)
12 – Stack fault (pushes an error code)
13 – General protection fault (pushes an error code)
14 – Page fault (pushes an error code)
15 – Unknown interrupt exception
16 – Co-processor fault
17 – Alignment check exception
18 – Machine check exception
19-31 – Reserved
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See: Intel\u00ae 64 and IA-32 Architectures Software Developer\u2019s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide – 6.3.1 External Interrupts<\/em>
WR Pin: This pin connects to a write strobe signal (One of 8 on a Pentium)
RD Pin: This connects to the IOCR (Input Output Control Routine) signal.
INT Pin: Connects to the INTR pin on the microprocessor.
INTA Pin: Connects to the INTA pin on the microprocessor.
A0 Pin: Selects different Command WORDS
CS Pin: Enables the chip for programming and control.
SP\/EN Pin: Slave program (SP) \/ Enable Buffer (EN).
Slave Program (1=Master, 0=Slave)
Enable Buffer (Controls data bus transievers when in buffered mode)
CAS0, CAS1, CAS2 Pins: Used to output from master to slave PIC controllers in cascaded systems.
D0 – D7 Pins: 8 bit Data connector pins.<\/p>\n\n\n\n

x86 Hardware Interrupts<\/th><\/tr>
8259A Input pin<\/td>Interrupt Number<\/td>Description<\/td><\/tr>
IRQ0<\/td>0x08<\/td>Timer<\/td><\/tr>
IRQ1<\/td>0x09<\/td>Keyboard<\/td><\/tr>
IRQ2<\/td>0x0A<\/td>Cascade for 8259A Slave controller<\/td><\/tr>
IRQ3<\/td>0x0B<\/td>Serial port 2<\/td><\/tr>
IRQ4<\/td>0x0C<\/td>Serial port 1<\/td><\/tr>
IRQ5<\/td>0x0D<\/td>AT systems: Parallel Port 2. PS\/2 systems: reserved<\/td><\/tr>
IRQ6<\/td>0x0E<\/td>Diskette drive<\/td><\/tr>
IRQ7<\/td>0x0F<\/td>Parallel Port 1<\/td><\/tr>
IRQ8\/IRQ0<\/td>0x70<\/td>CMOS Real time clock<\/td><\/tr>
IRQ9\/IRQ1<\/td>0x71<\/td>CGA vertical retrace<\/td><\/tr>
IRQ10\/IRQ2<\/td>0x72<\/td>Reserved<\/td><\/tr>
IRQ11\/IRQ3<\/td>0x73<\/td>Reserved<\/td><\/tr>
IRQ12\/IRQ4<\/td>0x74<\/td>AT systems: reserved. PS\/2: auxiliary device<\/td><\/tr>
IRQ13\/IRQ5<\/td>0x75<\/td>FPU<\/td><\/tr>
IRQ14\/IRQ6<\/td>0x76<\/td>Hard disk controller<\/td><\/tr>
IRQ15\/IRQ7<\/td>0x77<\/td>Reserved<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

8259A Registers<\/strong><\/p>\n\n\n\n