Tag Archives: hardware

PIC–ing

Ref: www.jamesmolloy.co.uk https://wiki.osdev.org/8259_PIC / http://www.brokenthorn.com/Resources/OSDevPic.html

The IBM PC 8259 PIC Architecture
In the beginning (IBM PC and XT), only a single 8259 PIC chip was used, which provided 8 IRQs to the system. These were traditionally mapped by the BIOS to interrupts 8 to 15 (0x08 to 0x0F). It is unlikely that any of these single-PIC machines will be encountered these days.


The IBM PC/AT 8259 PIC Architecture
The IBM PC/AT extended the PC architecture by adding a second 8259 PIC chip. This was possible due to the 8259A’s ability to cascade interrupts, that is, have them flow through one chip and into another. This gives a total of 15 interrupts. Why 15 and not 16? That’s because when you cascade chips, the PIC needs to use one of the interrupt lines to signal the other chip.
The low-level concepts behind external interrupts are not very complex. All devices that are interrupt-capable have a line connecting them to the PIC (programmable interrupt controller). The PIC is the only device that is directly connected to the CPU’s interrupt pin. It is used as a multiplexer, and has the ability to prioritize between interrupting devices. It is, essentially, a glorified 8-1 multiplexer. At some point, someone somewhere realized that 8 IRQ lines just wasn’t enough, and they daisy-chained another 8-1 PIC beside the original. So in all modern PCs, you have 2 PICs, the master and the slave, serving a total of 15 interruptable devices (one line is used to signal the slave PIC).
Only hardware interrupts are handled through the Programmable Interrupt Controller. The special, CPU-dedicated interrupts are shown below.

0 – Division by zero exception
1 – Debug exception
2 – Non maskable interrupt
3 – Break-point exception
4 – ‘Into detected overflow’
5 – Out of bounds exception
6 – Invalid opcode exception
7 – No co-processor exception
8 – Double fault (pushes an error code)
9 – Co-processor segment overrun
10 – Bad TSS (pushes an error code)
11 – Segment not present (pushes an error code)
12 – Stack fault (pushes an error code)
13 – General protection fault (pushes an error code)
14 – Page fault (pushes an error code)
15 – Unknown interrupt exception
16 – Co-processor fault
17 – Alignment check exception
18 – Machine check exception
19-31 – Reserved

See: Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide – 6.3.1 External Interrupts
WR Pin: This pin connects to a write strobe signal (One of 8 on a Pentium)
RD Pin: This connects to the IOCR (Input Output Control Routine) signal.
INT Pin: Connects to the INTR pin on the microprocessor.
INTA Pin: Connects to the INTA pin on the microprocessor.
A0 Pin: Selects different Command WORDS
CS Pin: Enables the chip for programming and control.
SP/EN Pin: Slave program (SP) / Enable Buffer (EN).
Slave Program (1=Master, 0=Slave)
Enable Buffer (Controls data bus transievers when in buffered mode)
CAS0, CAS1, CAS2 Pins: Used to output from master to slave PIC controllers in cascaded systems.
D0 – D7 Pins: 8 bit Data connector pins.

x86 Hardware Interrupts
8259A Input pinInterrupt NumberDescription
IRQ00x08Timer
IRQ10x09Keyboard
IRQ20x0ACascade for 8259A Slave controller
IRQ30x0BSerial port 2
IRQ40x0CSerial port 1
IRQ50x0DAT systems: Parallel Port 2. PS/2 systems: reserved
IRQ60x0EDiskette drive
IRQ70x0FParallel Port 1
IRQ8/IRQ00x70CMOS Real time clock
IRQ9/IRQ10x71CGA vertical retrace
IRQ10/IRQ20x72Reserved
IRQ11/IRQ30x73Reserved
IRQ12/IRQ40x74AT systems: reserved. PS/2: auxiliary device
IRQ13/IRQ50x75FPU
IRQ14/IRQ60x76Hard disk controller
IRQ15/IRQ70x77Reserved

8259A Registers

  • Command Register – This is a write only register that is used to send commands to the microcontroller.
  • Status register – This is a read only register that can be accessed to determin the status of the PIC.
  • Interrupt Request Register (IRR) – This register specifies which interrupts are pending acknowledgment. Note: This register is internal, and cannot be accessed directly.
  • In-Sevice Register (ISR) – This register specifies which interrupts have already been acknowledged, but are awaiting for the End of Interrupt (EOI) signal.
  • Interrupt Mask Register (IMR) – This specifies what interrupts are to be ignored, and not acknowledged.

Programming with the 8259 PIC
When the computer boots, the default interrupt mappings are:
IRQ 0..7 – INT 0x8..0xF
IRQ 8..15 – INT 0x70..0x77
Each chip (master and slave) has a command port and a data port (given in the table below). When no command is issued, the data port allows us to access the interrupt mask of the 8259 PIC.

Chip – Purpose I/O port
Master PIC -Command0x0020
Master PIC – Data0x0021
Slave PIC -Command0x00A0
Slave PIC – Data0x00A1

8253/8254 PIT – Programmable Interval Time

Original source: http://heim.ifi.uio.no/~stanisls/helppc/8253.html

Spec documentation:  8254 PROGRAMMABLE INTERVAL TIMER

Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
Port 42h, 8253 Counter 2 Cassette and Speaker Functions
Port 43h, 8253 Mode Control Register, data format:
	|7|6|5|4|3|2|1|0|  Mode Control Register
	 | | | | | | | `---- 0=16 binary counter, 1=4 decade BCD counter
	 | | | | `--------- counter mode bits
	 | | `------------ read/write/latch format bits
	 `--------------- counter select bits (also 8254 read back command)
Bits
76 Counter Select Bits
00 select counter 0
01 select counter 1
10 select counter 2
11 read back command (8254 only, illegal on 8253, see below)
Bits
54 Read/Write/Latch Format Bits
00 latch present counter value
01 read/write of MSB only
10 read/write of LSB only
11 read/write LSB, followed by write of MSB
Bits
321 Counter Mode Bits
000 mode 0, interrupt on terminal count; countdown, interrupt,

then wait for a new mode or count; loading a new count in the
middle of a count stops the countdown

001 mode 1, programmable one-shot; countdown with optional

restart; reloading the counter will not affect the countdown
until after the following trigger

010 mode 2, rate generator; generate one pulse after ‘count’ CLK

cycles; output remains high until after the new countdown has
begun; reloading the count mid-period does not take affect
until after the period

011 mode 3, square wave rate generator; generate one pulse after

‘count’ CLK cycles; output remains high until 1/2 of the next
countdown; it does this by decrementing by 2 until zero, at
which time it lowers the output signal, reloads the counter
and counts down again until interrupting at 0; reloading the
count mid-period does not take affect until after the period

100 mode 4, software triggered strobe; countdown with output high

until counter zero; at zero output goes low for one CLK
period; countdown is triggered by loading counter; reloading
counter takes effect on next CLK pulse

101 mode 5, hardware triggered strobe; countdown after triggering

with output high until counter zero; at zero output goes low
for one CLK period
Read Back Command Format (8254 only)
	|7|6|5|4|3|2|1|0| Read Back Command (written to Mode Control Reg)
	 | | | | | | | `--- must be zero
	 | | | | | | `---- select counter 0
	 | | | | | `----- select counter 1
	 | | | | `------ select counter 2
	 | | | `------- 0 = latch status of selected counters
	 | | `-------- 0 = latch count of selected counters
	 `----------- 11 = read back command
Read Back Command Status (8254 only, read from counter register)
	|7|6|5|4|3|2|1|0|  Read Back Command Status
	 | | | | | | | `--- 0=16 binary counter, 1=4 decade BCD counter
	 | | | | `-------- counter mode bits (see Mode Control Reg above)
	 | | `----------- read/write/latch format (see Mode Control Reg)
	 | `------------ 1=null count (no count set), 0=count available
	 `------------- state of OUT pin (1=high, 0=low)
  • the 8253 is used on the PC & XT, while the 8254 is used on the AT+
  • all counters are decrementing and fully independent
  • the PIT is tied to 3 clock lines all generating 1.19318 MHz.
  • the value of 1.19318MHz is derived from (4.77/4 MHz) and has it’s roots based on NTSC frequencies
  • counters are 16 bit quantities which are decremented and then tested against zero. Valid range is (0-65535). To get a value
    of 65536 clocks you must specify 0 as the default count since
    65536 is a 17 bit value.
  • reading by latching the count doesn’t disturb the countdown but reading the port directly does; except when using the 8254 Read
    Back Command
  • counter 0 is the time of day interrupt and is generated approximately 18.2 times per sec. The value 18.2 is derived from
    the frequency 1.10318/65536 (the normal default count).
  • counter 1 is normally set to 18 (dec.) and signals the 8237 to do a RAM refresh approximately every 15æs
  • counter 2 is normally used to generate tones from the speaker but can be used as a regular counter when used in conjunction
    with the 8255
  • newly loaded counters don’t take effect until after a an output pulse or input CLK cycle depending on the mode
  • the 8253 has a max input clock rate of 2.6MHz, the 8254 has max input clock rate of 10MHz

Programming considerations:

1. load Mode Control Register
2. let bus settle (jmp $+2)
3. write counter value
4. if counter 0 is modified, an INT 8 handler must be written to

call the original INT 8 handler every 18.2 seconds. When it
does call the original INT 8 handler it must NOT send and EOI
to the 8259 for the timer interrupt, since the original INT 8
handler will send the EOI also.

Example code:

	countdown  equ	8000h ; approx 36 interrupts per second
	   cli
	   mov	al,00110110b  ; bit 7,6 = (00) timer counter 0
				  ; bit 5,4 = (11) write LSB then MSB
				  ; bit 3-1 = (011) generate square wave
				  ; bit 0 = (0) binary counter
	   out	43h,al	      ; prep PIT, counter 0, square wave&init count
	   jmp	$+2
	   mov	cx,countdown  ; default is 0x0000 (65536) (18.2 per sec)
				  ; interrupts when counter decrements to 0
	   mov	al,cl	      ; send LSB of timer count
	   out	40h,al
	   jmp	$+2
	   mov	al,ch	      ; send MSB of timer count
	   out	40h,al
	   jmp	$+2

Reference Page

Reference Books

8254 PROGRAMMABLE INTERVAL TIMER (PIT) a counter/timer device designed to solve the common timing control problems in microcomputer
system design.

8259A Programmable Interrupt Controller (PIC) handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry.

Calling conventions for different C++ compilers and operating systems by Agner Fog, 2018

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FAT32 File System Specification FAT: General Overview of On-Disk Format
Version 1.03, December 6, 2000 Microsoft Corporation

How to Make a Computer Operating System by Samy Pessé

How It Works — CHS Translation Plus BIOS Types, LBA and Other Good Stuff Version 4a by Hale Landis (landis@sugs.tware.com)

Installable File Systems For OS/2 Version 3.0 OS/2 File Systems Department
PSPC Boca Raton, Florida February 13, 1998

Intel Microprocessors Architecture, Programming, and Interfacing, Eighth Edition, BARRY B. BREY

Microsoft Macro Assembler Reference MASM reference guide

Operating Systems, Internals and Design Principals 11th Edition William Stallings

PC DOS 7 Technical Update Document Number GG24-4459-00 February 1995

PS/2 Model 25 Technical Reference June 1987

PS2_Model_80_Technical_Reference October 90

Python for Developers First edition in English

The little book about OS development Erik Helin, Adam Renberg 2015-01-19

VESA BIOS EXTENSION (VBE) Core Functions Standard Version: 2.0 Document Revision: 1.1 Ratification Date: November 18, 1994

VGA BIOS OEM Reference Guide Revision 1.0 July 1999

Writing OS/2 Warp Device Drivers in C Third Edition

Writing a Simple Operating System — from Scratch by Nick Blundell

Libraries

OS/2 2.x Programming Documentation Books

OS/2 Museum – OS/2 2.0 Technical Library

Git Repos

OS2World  OS/2 Warp, ArcaOS and eComStation public source code

OS2World/SYSTEM-LOADER-QSINIT  QSINIT is a replacement of OS2LDR created from scratch.

Microsoft Github

trac.netlabs.org – OS/2 Available Projects